The present invention relates generally to physical design and fabrication of semiconductor integrated circuits, and more particularly, to metal fill during IC layout and design.
Integrated circuit (IC) physical design has become increasingly complex as the number of devices on a chip increases and device size decreases. ICs also have an increasing number of layers, including metal layers for routing signals and dielectric layers separating the metal layers. Non-planarity can negatively affect device yields and the effect of non-planarity in one layer can be compounded across other layers. It is well known to use chemical mechanical polishing (CMP) for planarization of dielectric layers during fabrication. However, CMP is impacted by non-planarities in the metal layers. One way to address metal layer non-planarity is by “metal fill”. In metal fill, open areas within each metal layer are filled with a metal pattern. However, it is known that rather than just performing indiscriminate metal filling to meet metal density requirements, metal fill can also be used to improve chip performance, such as by reducing cross coupling capacitance as taught by U.S. Pat. No. 8,753,900.
FIG. 1 shows a conventional IC design and fabrication process. At step 10, IC design is performed by an IC designer to meet the functional requirements of the chip specification and a design file or netlist is prepared. At step 12, place and route are performed using electronic design automation (EDA) tools, where the various circuit blocks (sometimes referred to as IPs) and their interconnections, as specified in the design file, are placed within the chip boundaries and signals interconnecting the blocks are routed, and then timing analysis is performed. Place and route and its sub-steps may be re-iterated until the design meets timing requirements. At step 14, metal filling is performed, which generally means that empty spaces within the metal layers are filled with metal in order to meet minimum metal density requirements and in addition, as noted above, to possibly improve cross coupling capacitance. The metal fill patterns are determined by algorithms within the EDA tools. After metal fill, a GDS (Graphic Design System) file is prepared (i.e., tape-out) and sent to a manufacturer so that the chip can be fabricated. An example of an EDA tool for conducting place and route, metal fill, and generating the GDS file is Cadence® Encounter®.
System on Chips (SoCs) often include various analog blocks, memories, multi-cores and multi-power domains, and require a sophisticated power grid to deliver the correct amount of power to the correct domains. All of these differing power requirements can cause the power grid to be discontinuous at many places during the design stage. The power required by a SoC is also effected by limited numbers of power and ground pins.
It would be advantageous if metal fill could be used to not only meet metal layer density requirements, but also to take into account and help meet circuit power requirements.